A sigma-delta analog-digital converter (ADC) oversamples a desired signal by a large factor and then filters the desired signal band with a decimation filter. Incremental analog-digital converters (IADCs) are a subclass of sigma-delta ADCs that are operated intermittently and exhibit high accuracy with low power dissipation. IADCs are frequently used in sensor and micro-electro-mechanical system (MEMS) interfaces.
IADCs are commonly implemented with single-bit quantizers, which limit the resolution and speed. When IADCs are implemented with multi-bit quantizers, the performance is largely improved by increasing the conversion rate and resolution of an ADC.
A decimation filter follows the IADC and reduces the sampling rate and filters off unwanted noise signal. Traditional decimation filters occupy a large area and consume a great amount of power. This is particularly true with IADCs implemented with multi-bit quantizers. When the quantizer level “M” increases, the decimation filter and post processing circuit's power demand and size increases.
Conventional methods for decimation filtering require a number of physical sub decimation filters “N” equal to the total number of quantizer levels “M.” Therefore, it may be desired to create a power and area efficient decimation filter that allows the use of an optimized power efficient analog modulator, reduced chip thermal budget, and reduced chip area for lower cost.